In 3D high density memory, a vertical array where the word lines run horizontally and the bit lines run vertically (or vice versa) is preferred over a cross-point array where both word lines and bit lines run horizontally. For example, in a vertical array, the word lines run in a plane that is perpendicular to the plane of the bit lines, while in a cross point array the word lines and bit lines run in the same or parallel planes. A 3D vertical array can be formed by etching through multiple deposited layers together, which can significantly reduce manufacturing cost. In contrast, a 3D cross-point array requires a pattern-etch process performed layer by layer, and thus the manufacturing costs are higher.
One problem associated with implementing a 3D array is referred to as a “sneak leakage path” problem. A sneak leakage path allows current to flow on a word line associated with an off memory cell. Though there are techniques to address this problem in 3D cross point arrays, an effective solution for 3D vertical arrays is desired.
FIG. 1A shows a conventional vertical cell string structure having a horizontal electrode (word line) 101, a vertical electrode (bit line) 102, and a selector 103. The selector 103 is used to control current flow direction on the word lines. A typical selector may be a P-N diode, Schottky diode, or other material with threshold behavior for current flow direction. Also shown is a memory element 104, which may be resistive switching material, phase-change material, and/or others depending on the memory type.
Unfortunately, this conventional vertical cell structure exhibits the ‘sneak leakage path’ problem. Because this cell's selector layer 103 is connected to adjacent cells and the selector is normally a conductor, current can leak through the selector layer 103 to an unselected cell's word line, which is defined as sneak path leakage.
FIG. 1B shows a cross-sectional view of the conventional vertical cell structure shown in FIG. 1A taken at cross-section line 110. As shown in FIG. 1B, there are three horizontal word lines 101a, 101b, and 101c and one vertical bit line 102. Assuming a selected cell on word line 101b is an off cell, the memory element 105 has very high resistance. Because the selector layer 103 is a conductor, current can leak (as shown at path 109) from the bit line 102 through the selector layer 103 from an adjacent on-cell on word line 101a to the word line 101b of the off-cell, and thus cause read errors. For example, the current path 109 shows how current may flow from the bit linen 102 through the selector 103 to the unselected word line 101b due to the sneak leakage path problem.
FIG. 2A shows another conventional vertical cell structure having a horizontal electrode (word line) 201, a vertical electrode (bit line) 202, a selector 203, and a memory 204. FIG. 2B shows a cross-sectional view of the vertical cell structure shown in FIG. 2A taken at cross-section line 210. Similar to the cell structure shown in FIG. 1B, the sneak leakage path problem can exist in the cell structure shown in FIG. 2B as well. For example, referring to FIG. 2B, the cell structure includes horizontal word lines 201a, 201b, and 201c and one vertical bit line 202. It will be assumed that a cell on word line 201b is an off cell such that memory element 205 has very high resistance. Due to the fact that selector layer 203 is a conductor, the current can leak (as show at path 209) from the bit line 202 through the selector layer 203 from an adjacent on-cell on word line 201a to the word line 201b of the off-cell, and thus cause read errors.
Therefore, it is desirable to have cell structures and process flows to form 3D vertical memory arrays to eliminate or reduce the sneak leakage path problem.